Index: drivers/mtd/nand/mvebu_nfc/hal/mvNfc.c
===================================================================
--- drivers/mtd/nand/mvebu_nfc/hal/mvNfc.c	(revision 3)
+++ drivers/mtd/nand/mvebu_nfc/hal/mvNfc.c	(working copy)
@@ -274,6 +274,144 @@
 
 /* Defined Flash Types */
 MV_NFC_FLASH_INFO flashDeviceInfo[] = {
+   {			/* Hynix 4Gb */
+	.tADL = 70,		/* tADL, Address to write data delay */
+	.tCH = 5,		/* tCH, Enable signal hold time */
+	.tCS = 20,		/* tCS, Enable signal setup time */
+	.tWC = 25,		/* tWC, ND_nWE cycle duration */
+	.tWH = 10,		/* tWH, ND_nWE high duration */
+	.tWP = 12,		/* tWP, ND_nWE pulse time */
+	.tRC = 25,		/* tWC, ND_nRE cycle duration */
+	.tRH = 10,		/* tRH, ND_nRE high duration */   //BLUE_ADD , this item not sure
+	.tRP = 12,		/* tRP, ND_nRE pulse width */
+	.tR = 25000,		/* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read - 25000+20+100+1 */
+	.tWHR = 60,		/* tWHR, ND_nWE high to ND_nRE low delay for status read */
+	.tAR = 10,		/* tAR, ND_ALE low to ND_nRE low delay */
+	.tRHW = 100,		/* tRHW, ND_nRE high to ND_nWE low delay */
+	.pgPrBlk = 64,		/* Pages per block - detected */
+	.pgSz = 2048,		/* Page size */
+	.oobSz = 64,		/* Spare size */
+	.blkNum = 4096,		/* Number of blocks/sectors in the flash */
+	.id = 0xDCAD,		/* Device ID 0xDevice,Vendor */
+	.model = "Hynix H27(U_S)4G8 4Gb 8bit",
+	.bb_page = 63,		/* Manufacturer Bad block marking page in block */
+	.flags = NFC_CLOCK_UPSCALE_200M
+	},
+	{			/* Hynix 2Gb */
+	.tADL = 70,		/* tADL, Address to write data delay */
+	.tCH = 5,		/* tCH, Enable signal hold time */
+	.tCS = 20,		/* tCS, Enable signal setup time */
+	.tWC = 25,		/* tWC, ND_nWE cycle duration */
+	.tWH = 10,		/* tWH, ND_nWE high duration */
+	.tWP = 12,		/* tWP, ND_nWE pulse time */
+	.tRC = 25,		/* tWC, ND_nRE cycle duration */
+	.tRH = 10,		/* tRH, ND_nRE high duration */   //BLUE_ADD , this item not sure
+	.tRP = 12,		/* tRP, ND_nRE pulse width */
+	.tR = 25000,		/* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read - 25000+20+100+1 */
+	.tWHR = 60,		/* tWHR, ND_nWE high to ND_nRE low delay for status read */
+	.tAR = 10,		/* tAR, ND_ALE low to ND_nRE low delay */
+	.tRHW = 100,		/* tRHW, ND_nRE high to ND_nWE low delay */
+	.pgPrBlk = 64,		/* Pages per block - detected */
+	.pgSz = 2048,		/* Page size */
+	.oobSz = 64,		/* Spare size */
+	.blkNum = 2048,		/* Number of blocks/sectors in the flash */
+	.id = 0xDAAD,		/* Device ID 0xDevice,Vendor */
+	.model = "Hynix H27(U_S)2G8 2Gb 8bit",
+	.bb_page = 63,		/* Manufacturer Bad block marking page in block */
+	.flags = NFC_CLOCK_UPSCALE_200M
+	},
+	{			/* MXIC 2Gb */
+	.tADL = 70,		/* tADL, Address to write data delay */
+	.tCH = 5,		/* tCH, Enable signal hold time */
+	.tCS = 15,		/* tCS, Enable signal setup time */
+	.tWC = 20,		/* tWC, ND_nWE cycle duration */
+	.tWH = 7,		/* tWH, ND_nWE high duration */
+	.tWP = 10,		/* tWP, ND_nWE pulse time */
+	.tRC = 20,		/* tWC, ND_nRE cycle duration */
+	.tRH = 10,		/* tRH, ND_nRE high duration */   //BLUE_ADD , this item not sure
+	.tRP = 10,		/* tRP, ND_nRE pulse width */
+	.tR = 25000,		/* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read - 25000+20+100+1 */
+	.tWHR = 60,		/* tWHR, ND_nWE high to ND_nRE low delay for status read */
+	.tAR = 10,		/* tAR, ND_ALE low to ND_nRE low delay */
+	.tRHW = 60,		/* tRHW, ND_nRE high to ND_nWE low delay */
+	.pgPrBlk = 64,		/* Pages per block - detected */
+	.pgSz = 2048,		/* Page size */
+	.oobSz = 64,		/* Spare size */
+	.blkNum = 2048,		/* Number of blocks/sectors in the flash */
+	.id = 0xDAC2,		/* Device ID 0xDevice,Vendor */
+	.model = "MXIC MX30LF2G18AC 2Gb 8bit",
+	.bb_page = 63,		/* Manufacturer Bad block marking page in block */
+	.flags = NFC_CLOCK_UPSCALE_200M
+	},	
+	{                       /* ESMT F59L2G81A 2Gb, BLUE_ADD */
+    .tADL = 100,             /* tADL, Address to write data delay */
+    .tCH = 5,               /* tCH, Enable signal hold time */
+    .tCS = 20,              /* tCS, Enable signal setup time */
+    .tWC = 25,              /* tWC, ND_nWE cycle duration */
+    .tWH = 10,              /* tWH, ND_nWE high duration */
+    .tWP = 12,              /* tWP, ND_nWE pulse time */
+    .tRC = 25,              /* tWC, ND_nRE cycle duration */
+    .tRH = 10,              /* ? tRH, ND_nRE high duration */
+    .tRP = 12,              /* tRP, ND_nRE pulse width */
+    .tR = 25000,            /* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read - 25000+20+100+1 */
+    .tWHR = 60,             /* tWHR, ND_nWE high to ND_nRE low delay for status read */
+    .tAR = 10,              /* tAR, ND_ALE low to ND_nRE low delay */
+    .tRHW = 100,            /* tRHW, ND_nRE high to ND_nWE low delay */
+    .pgPrBlk = 64,          /* Pages per block - detected */
+    .pgSz = 2048,           /* Page size */
+    .oobSz = 64,            /* Spare size */
+    .blkNum = 2048,         /* Number of blocks/sectors in the flash */
+    .id = 0xDAC8,           /* Device ID 0xDevice,Vendor */
+    .model = "ESMT F59L2G81A 2Gb 8bit",
+    .bb_page = 63,          /* Manufacturer Basdad block marking page in block */
+    .flags = NFC_CLOCK_UPSCALE_200M
+    },	
+   {                       /* Mxic 4Gb */
+    .tADL = 70,              /* tADL, Address to write data delay */
+    .tCH = 5,          /* tCH, Enable signal hold time */
+    .tCS = 15,         /* tCS, Enable signal setup time */
+    .tWC = 20,               /* tWC, ND_nWE cycle duration */
+    .tWH = 7,         /* tWH, ND_nWE high duration */
+    .tWP = 10,               /* tWP, ND_nWE pulse time */
+    .tRC = 20,                /* tWC, ND_nRE cycle duration */
+    .tRH = 7,          /* tRH, ND_nRE high duration */
+    .tRP = 10,         /* tRP, ND_nRE pulse width */
+    .tR = 25000,             /* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read - 25000+20+100+1 */
+    .tWHR = 60,             /* tWHR, ND_nWE high to ND_nRE low delay for status read */
+    .tAR = 10,                /* tAR, ND_ALE low to ND_nRE low delay */
+    .tRHW = 60,           /* tRHW, ND_nRE high to ND_nWE low delay */
+    .pgPrBlk = 64,          /* Pages per block - detected */
+    .pgSz = 2048,           /* Page size */
+    .oobSz = 64,             /* Spare size */
+    .blkNum = 4096,              /* Number of blocks/sectors in the flash */
+    .id = 0xDCC2,          /* Device ID 0xDevice,Vendor */
+    .model = "Micron 4Gb 8bit",
+    .bb_page = 63,                /* Manufacturer Bad block marking page in block */
+    .flags = NFC_CLOCK_UPSCALE_200M
+    },
+	{                       /* spansion 4Gb */
+	.tADL = 70,              /* tADL, Address to write data delay */
+	.tCH = 5,          /* tCH, Enable signal hold time */
+	.tCS = 20,         /* tCS, Enable signal setup time */
+	.tWC = 25,               /* tWC, ND_nWE cycle duration */
+	.tWH = 10,               /* tWH, ND_nWE high duration */
+	.tWP = 12,               /* tWP, ND_nWE pulse time */
+	.tRC = 25,                /* tWC, ND_nRE cycle duration */
+	.tRH = 10,                /* tRH, ND_nRE high duration */
+	.tRP = 12,         /* tRP, ND_nRE pulse width */
+	.tR = 25000,             /* tR = data transfer from cell to register, maximum 60,000ns */
+	.tWHR = 60,             /* tWHR, ND_nWE high to ND_nRE low delay for status read */
+	.tAR = 10,                /* tAR, ND_ALE low to ND_nRE low delay */
+	.tRHW = 100,           /* tRHW, ND_nRE high to ND_nWE low delay 32 clocks */
+	.pgPrBlk = 64,          /* Pages per block - detected */
+	.pgSz = 2048,           /* Page size */
+	.oobSz = 64,             /* Spare size */
+	.blkNum = 2048,              /* Number of blocks/sectors in the flash */
+	.id = 0xdc01,            /* Device ID 0xDevice,Vendor */ /* 0x9AA8 when run through JTAG */
+	.model = "spansion 4Gb 8bit",
+	.bb_page = 0,          /* Manufacturer Bad block marking page in block */
+	.flags = NFC_CLOCK_UPSCALE_200M
+	},
 	{			/* Micron 4Gb */
 	.tADL = 70,		/* tADL, Address to write data delay */
 	.tCH = 5,		/* tCH, Enable signal hold time */